1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a nonvolatile memory device and a method of manufacturing the same.
2. Description of the Related Art
A nonvolatile semiconductor memory (NVSM) is categorized into a floating gate type or a metal insulator semiconductor (MIS) type in which two or more kinds of dielectric layers are stacked.
A floating type NVSM functions as a memory using potential wells, and an erasable programmable read only memory (EPROM) tunnel oxide (ETOX) structure is being widely used as a flash electrically erasable and programmable read only memory (flash EEPROM).
An MIS type NVSM functions as a memory using trap sites that exist between a dielectric layer and a bulk or between dielectric layers. Typically, the MIS type NVSM can be classified into a metal-oxide-nitride-oxide-silicon (MONOS) type, a silicon-oxide-nitride-oxide-silicon (SONOS) type, and the likes.
FIG. 1 is a cross-sectional view of a conventional NVSM having a MONOS or SONOS type structure.
Referring to FIG. 1, a source region 16S and a drain region 16D are disposed in a semiconductor substrate 11 and separated apart from each other. A tunnel oxide layer 12, a charge trapping layer 13, a blocking oxide layer 14, and a gate electrode 15 are sequentially stacked on a channel region 17 interposed between the source and drain regions 16S and 16D. Insulating spacers 18 are formed on the sidewalls of the stacked structure. The tunnel oxide layer 12 is formed of thermal oxide, the charge trapping layer 13 is formed of silicon nitride, and the blocking oxide layer 14 is formed of oxide using wet oxidation or chemical vapor deposition (CVD). In the case of the MONOS type, the gate electrode 15 is formed of a metal. In the case of the SONOS type, the gate electrode 15 is formed of doped polysilicon.
The programming and erasing of the conventional NVSM will be described now.
At the outset, during programming, if a sufficiently high positive (+) voltage is applied to the gate electrode 15, electrons emitted from the semiconductor substrate 11 tunnel the tunnel oxide layer 12 and are injected into the charge trapping layer 13. In this case, the blocking oxide layer 14 disposed on the charge trapping layer 13 prevents the electrons injected in the charge trapping layer 14 from leaking into the gate electrode 15 and also prevents injection of holes from the gate electrode 15 into the charge trapping layer 13. The electrons, which are injected into the charge trapping layer 13 through the tunnel oxide layer 12, are trapped in a bulk trap of the charge trapping layer 13 or in an interfacial trap between the charge trapping layer 13 and the blocking oxide layer 14, and a threshold voltage increases.
During erasing, by applying a negative (−) voltage to the gate electrode 15, the trapped electrons are emitted to the semiconductor substrate 11 so that a threshold voltage is reduced to the same value as before programming.
In recent years, with the developments in nanotechnologies, much research into the use of an NVSM and a 2-bit-per-cell NVSM using nano-crystals has been conducted.
FIG. 2 is a cross-sectional view of a conventional NVSM using nano-crystals.
Referring to FIG. 2, a source region 26S and a drain region 26D are disposed in a semiconductor substrate 21 and separated apart from each other. A tunnel oxide layer 22, a charge trapping layer 23, a blocking oxide layer 24, and a gate electrode 25 are sequentially stacked on a channel region 27 interposed between the source and drain regions 26S and 26D. Insulating spacers 28 are disposed on the sidewalls of the stacked structure. The charge trapping layer 23 is formed of clusters or dots having a size of several to several tens of nm, namely, nano-crystals 23NC.
A method of manufacturing the charge trapping layer 23 formed of the nano-crystals 23NC is disclosed in the following two papers.
(I) “A Silicon Nanocrystals Based Memory by Sandip Tiwari et al., Appl. Phys. Lett. 68(10) p. 1377(1996)”: A tunnel oxide layer having a thickness of 1.1 to 1.8 nm is formed on a semiconductor substrate in which source and drain regions are disposed. Nanocrystals having a diameter of 5 nm, which constitute a charge trapping layer, are formed on the tunnel oxide layer by a space of 5 nm using a CVD apparatus. The density of the nanocrystals is about 1×1012/cm−2. A 7-nm blocking oxide layer is formed on the charge trapping layer, and a gate electrode is formed on the blocking oxide layer.
(II) “Fast and Long Retention-Time nano-Crystal Memory by Hussein I. Hanafi et al., IEEE Trans. Electron Device, Vo1. 43, p. 1553(1996)”: A 5 to 20-nm oxide layer is formed on a semiconductor substrate. A high concentration of Si or Ge ions are implanted into the oxide layer and supersaturated. In this case, the ions are implanted with about 5 KeV and a dose of about 5×1015 ions/cm2. The doped oxide layer is annealed in an N2 atmosphere at 950° C. for 30 minutes, thereby growing Si or Ge nano-crystals in the oxide layer to a diameter of 5 nm. A source region and a drain region are formed in the semiconductor substrate and separated a predetermined distance apart from each other, and a gate electrode is formed on a portion of the oxide layer corresponding to a channel region interposed between the source and drain regions.
The conventional NVSMs using nano-crystals have the advantages of the foregoing conventional MONOS or SONOS type NVSMs. Also, charges, which are injected into nano-crystals of a charge trapping layer, cannot easily move between the nano-crystals. Accordingly, in comparison with the conventional MONOS or SONOS type NVSMs, NVSMs using nano-crystals can suppress lateral diffusion of charges, be effectively embodied as 2-bit-per-cell NVSMs, and be easily downscaled.
However, when a conventional NVSM using nano-crystals is embodied as a 2-bit-per-cell memory, it is very difficult to scale down the NVSM to a nanoscale or terascale ultrahigh-integrated device. For example, to manufacture a 2-bit-per-cell device, charges are partially injected into charge trapping layers adjacent to source and drain regions. In the case of a short channel, both a superposition effect and a lateral diffusion of charges occur during the injection of the charges, thus disturbing 2-bit-per-cell operations of the NVSM. To solve this problem, channel length should be maintained above a predetermined value. In this case, it is impossible to further scale down NVSMs and further increase the integration density thereof. Accordingly, the foregoing conventional NVSMs using nano-crystals cannot meet the requisitions of the next-generation semiconductor technologies, such as low voltage, subminiature size, ultrahigh integration, high performance, and high reliability.